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Adjusted addresses used in PRSwitchGetStates to reflect FPGA change. Use the combined version/revision to choose between the old address and the new one so that old FPGAs will still work fine.

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This commit is contained in:
Gerry Stellenberg
2011-06-07 09:00:18 -05:00
parent 0ce137fbc0
commit ed8f768ae2
3 changed files with 23 additions and 9 deletions
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25
src/PRDevice.cpp
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@@ -101,11 +101,6 @@ PRResult PRDevice::Reset(uint32_t resetFlags)
collected_bytes_wr_addr = 0;
num_collected_bytes = 0;
// Initialize Ver/Rev
version = 0;
revision = 0;
combinedVersionRevision = 0;
// Make sure the data queues are empty.
while (!unrequestedDataQueue.empty()) unrequestedDataQueue.pop();
while (!requestedDataQueue.empty()) requestedDataQueue.pop();
@@ -343,6 +338,7 @@ PRResult PRDevice::DriverLoadMachineTypeDefaults(PRMachineType machineType, uint
bool encodeEnables;
int rowEnableSelect;
int lastCoilDriverGroup;
switch (machineType)
{
@@ -394,6 +390,13 @@ PRResult PRDevice::DriverLoadMachineTypeDefaults(PRMachineType machineType, uint
lastCoilDriverGroup = lastSternCoilDriverGroup;
break;
}
default:
// Don't do anything for non-specific machine types. Enabling
// drivers and/or groups could be dangerous, especially if polarities
// are wrong.
return kPRSuccess;
}
memset(&driverGlobalConfig, 0x00, sizeof(PRDriverGlobalConfig));
@@ -738,8 +741,15 @@ PRResult PRDevice::SwitchGetStates( PREventType * switchStates, uint16_t numSwit
{
rc = RequestData(P_ROC_BUS_SWITCH_CTRL_SELECT,
P_ROC_SWITCH_CTRL_STATE_BASE_ADDR + i, 1);
rc = RequestData(P_ROC_BUS_SWITCH_CTRL_SELECT,
P_ROC_SWITCH_CTRL_DEBOUNCE_BASE_ADDR + i, 1);
if (combinedVersionRevision < P_ROC_VER_REV_FIXED_SWITCH_STATE_READS) {
rc = RequestData(P_ROC_BUS_SWITCH_CTRL_SELECT,
P_ROC_SWITCH_CTRL_OLD_DEBOUNCE_BASE_ADDR + i, 1);
}
else {
rc = RequestData(P_ROC_BUS_SWITCH_CTRL_SELECT,
P_ROC_SWITCH_CTRL_DEBOUNCE_BASE_ADDR + i, 1);
}
}
// Expect 4 words for each 32 switches. The state and debounce words,
@@ -1037,6 +1047,7 @@ PRResult PRDevice::VerifyChipID()
DEBUG(PRLog(kPRLogError, "FPGA Chip ID: 0x%x\n", buffer[1]));
revision = buffer[2] & 0xffff;
version = buffer[2] >> 16;
CalcCombinedVerRevision();
DEBUG(PRLog(kPRLogError, "FPGA Chip Version/Rev: %d.%d\n", version, revision));
DEBUG(PRLog(kPRLogInfo, "Watchdog Settings: 0x%x\n", buffer[3]));
DEBUG(PRLog(kPRLogInfo, "Switches: 0x%x\n", buffer[4]));

2
src/PRDevice.h
View File

@@ -140,7 +140,7 @@ protected:
uint16_t version;
uint16_t revision;
uint16_t combinedVersionRevision;
uint32_t combinedVersionRevision;
/**
* Calculated combined Version/Revision number.
*/

5
src/PRHardware.h
View File

@@ -47,6 +47,8 @@ const uint32_t P_ROC_INIT_PATTERN_A = 0x801F1122;
const uint32_t P_ROC_INIT_PATTERN_B = 0x345678AB;
const uint32_t P_ROC_CHIP_ID = 0xfeedbeef;
const uint32_t P_ROC_VER_REV_FIXED_SWITCH_STATE_READS = 0x10013; // 1.19
const uint32_t P_ROC_AUTO_STERN_DETECT_SHIFT = 8;
const uint32_t P_ROC_AUTO_STERN_DETECT_MASK = 0x00000100;
const uint32_t P_ROC_AUTO_STERN_DETECT_VALUE = 0x1;
@@ -122,7 +124,8 @@ const uint32_t P_ROC_JTAG_TDO_MEMORY_BASE_ADDR = 0x400;
const uint32_t P_ROC_JTAG_TDI_MEMORY_BASE_ADDR = 0x800;
const uint32_t P_ROC_SWITCH_CTRL_STATE_BASE_ADDR = 4;
const uint32_t P_ROC_SWITCH_CTRL_DEBOUNCE_BASE_ADDR = 11;
const uint32_t P_ROC_SWITCH_CTRL_OLD_DEBOUNCE_BASE_ADDR = 11;
const uint32_t P_ROC_SWITCH_CTRL_DEBOUNCE_BASE_ADDR = 12;
const uint32_t P_ROC_EVENT_TYPE_SWITCH = 0;
const uint32_t P_ROC_EVENT_TYPE_DMD = 1;